In the manufacture of integrated CMOS circuits having silicon gates it is difficult to simultaneously obtain a low threshold voltage and a small distance between the active drain and source regions in both transistors of the CMOS pair. Both of these characteristics are desirable for each transistor as they respectively enable the use of low supply voltages and the achievement of high integration densities and high speeds of response.
For an explanation of the measures which may be carried out in order to produce transistors having low threshold voltages, reference is made to the following relationship, quoted, for example, on page 333 of "Physics and Technology of Semiconductor Devices" by A. S. Grove, published by Wiley, which expresses, as a function of characteristic parameters, the threshold voltage of an MOS transistor: ##EQU1## In this relationship the minus sign (-) relates to a p-channel transistor, the plus sign (+) to an n-channel transistor. The reference symbols used have the following meanings:
V.sub.T =threshold voltage PA1 V.sub.FB =flat band voltage PA1 .phi..sub.s s=surface potential of the substrate PA1 K.sub.s =relative permittivity of silicon PA1 .epsilon..sub.o =electric constant PA1 q=electron charge PA1 N=concentration of doping agent in the region receiving the transistor PA1 Co=capacitance, per surface unit, of the gate dielectric.
The threshold voltage V.sub.T is negative for the p-channel transistors and positive for the N-channel transistors.
The value of the threshold voltage of a transistor depends on the three terms appearing in the second side of the relationship given above. In the n-channel transistor of a conventional CMOS device the two terms V.sub.FB and .phi..sub.s have opposite signs (V.sub.FB is negative and .phi..sub.s is positive) and offset one another almost totally, as a result of which the threshold voltage essentially depends on the third term which may cause V.sub.T to assume the desired value by variation. On the other hand, in the case of the p-channel transistor of CMOS device the terms V.sub.FB and .phi..sub.s are both negative and the third term, which is positive, is preceded by the minus sign, as a result of which all three terms have a non-negligible effect on the value of V.sub.T and, if solely the third term varies, the absolute value of V.sub.T may not drop below .vertline.V.sub.FB +.phi..sub.s .vertline..
In the CMOS devices constructed in accordance with the prior art, the third term is reduced in order to lower the threshold voltage of both transistors, in particular by reducing the N (concentrationof doping agent in the region receiving the n-channel transistor and in the region receiving the p-channel transistor). In the n-channel transistor, as V.sub.T depends essentially on the third term, a small reduct'on of the N (concentration of doping agent) is sufficient to obtain a significant reduction of the threshold voltage. On the other hand, in the p-channel transistor it is necessary to considerably decrease the N (concentration of doping agent) in order to obtain a substantial reduction of V.sub.T However, in doing this, a drawback arises. In effect, by considerably reducing the concentration of doping agent in the substrate of the p-channel transistor there may arise, under certain drain and source polarization conditions, the formation of a deep conductive channel even at gate voltages which are lower than the threshold voltage (phenomenon known as punch-through) as a result of which it is impossible to control the transistor. This drawback is avoided by increasing the distance between the drain and source regions of the p-channel transistor. This measure involves, however, an increase in the length of this transistor and therefore a decrease in integration density and in the speed of response.
In order to reduce the value of the threshold voltage of the p-channel transistor of a CMOS device, it is possible to act on the flat band voltage V.sub.FB. As mentioned above, V.sub.FB is negative, whereas it is advisable for it to be positive for a substantial decrease in the value of V.sub.T. As known to persons skilled in the art, the flat band voltage is roughly proportional to the difference between the Fermi energy of the substrate receiving the transistor and the Fermi energy of the gate electrode. In a p-channel transistor, the substrate is of n-type, as a result of which the relative Fermi level is displaced towards the conduction band, i.e. towards high energy levels, and when this transistor forms part of a CMOS device with polycrystalline silicon gate electrodes, the polycrystalline silicon is normally of N+ type, as a result of which the relative Fermi level is even closer to the conduction band of that of the substrate. The Fermi energy of the substrate :s therefore lower than the Fermi energy of the gate electrode and the flat band voltage assumes a negative voltage, typically of approximately - 250 mV. In order to bring it to a sufficiently high positive value, for example approximately 750 mV, the Fermi level of the gate electrode must be displaced towards the valency band, i.e. towards energy levels lower than that of the substrate and in order to do this the polycrystalline silicon must be heavily doped with p-type impurities (P+).
If a positive flat band voltage is used for the p-channel transistor, a sufficiently low threshold voltage is obtained, even with a relatively high concentration of doping agent in the substrate. This solution is therefore particularly advantageous in that it enables the achievement of a p-channel transistor having both a low threshold voltage and a small distance between the active regions.
However, if the gate electrodes of the p-channel transistors are doped with impurities of p-type and the n-channel transistors with impurities of n-type it is not possible to directly connect polycrystalline silicon electrodes belonging to complementary transistors, for example the gate electrodes of a CMOS inverter, since a diode is produced if two electrodes doped with impurities of opposite types are connected together. This drawback may be avoided if the electrodes are connected by a higher metallization layer, the construction of which is, however also disadvantageous as it requires the use of relatively extensive areas and makes the circuit design less flexible, as a result of which this system has not been used in practice and the polycrystalline silicon of both the transistors of the CMOS is doped with impurities of a single type of conductivity, i.e. of n-type.
By doping part of the polycrystalline silicon of :he CMOS device with an acceptor element a further considerable advantage is obtained, i.e. the possibility of providing direct contacts between the polycrystalline silicon and the substrate regions both of n and p-type, for example the active drain regions of the two transistors, whilst in the devices of the prior art, as all the polycrystalline silicon is of n-type, this is only possible for the n-type regions. This situation is particularly advantageous as the direct contacts enable a saving of space and therefore greater miniaturization of the devices with respect to the contacts by means of metal interconnections.